chipsec.modules.common.pscs.ppin_ctl_lock moduleΒΆ

Protected Processor Inventory Number Enable Control (PPIN_CTL) MSR Lock Test

This module will verify that the Protected Processor Inventory Number Enable Control MSR lock is set.

Reference:

Intel SDM Vol4 Xeon E5 V2 : Section 2.11.1 Xeon E5 V4 : Section 2.15 Xeon Scalable Family : Section 2.16.3 Xeon PHI : Section 2.17 ADL FAS : Section 13.12.2

Usage:

chipsec_main -m common.pscs.ppin_ctl_lock

Example:
>>> chipsec_main.py -m common.pscs.ppin_ctl_lock

Note

  • MSR_PPIN_CTL.LOCK must be defined for the platform for this module to run.

  • MSR_PLATFORM_INFO.PPIN_CAP must be defined for the platform for this module to run.

Note

Unfortunately, this requirement is missing from most PSCS documents.